The present invention is related in general to the field of electronic circuits, and more specifically to an apparatus and method for reducing current leakage in a phase locked loop (PLL).
A PLL is a well-known electronic circuit used in many semiconductor devices. A PLL is a closed loop feedback control circuit which provides an output signal that is locked in phase and frequency of an input signal used as a reference. The PLL typically includes a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage-controlled oscillator (VCO), and an optional divider. The PFD compares a feedback signal received from the divider with a reference signal and generates an error signal, which is proportional to the magnitude of the phase/frequency difference between them. The error signal is provided to the CP. In some PLL circuits, the functionality of the CP may be combined with the PFD. The CP provides a current output, which is typically output in the form of current pulses in response to a positive or negative error signal. The current output of the CP controls a magnitude of the charge stored in the loop filter, thus converting the output of the PFD to a control voltage input recognizable by the VCO. The VCO generates an output frequency signal proportional to the control voltage input. The output frequency signal may be optionally further divided down by the divider before being fed back to the PFD. When the PLL is in a “locked” state, there is a constant phase difference (usually zero) between the feedback signal and a reference signal and their frequencies are matched.
Active compensation circuits for the loop filter (or in some cases the CP) have been included in the PLL to increase its performance measured in terms of an improved loop stability, increased gain, narrower loop bandwidth, and higher noise immunity compared to traditional charge pump compensation methods. One such active compensation based PLL circuit (also referred to as an active compensation PLL) is described in further detail in the following U.S. patent, which is hereby incorporated by reference into this specification: U.S. Pat. No. 6,611,176 entitled ‘Method and apparatus for two zeros/two poles active compensation phase locked loops’. A key limitation in many traditional active compensation PLL circuits is a presence of higher than tolerable current leakage. This phenomenon is often detrimental to the PLL performance.